Algorithm
Efficient memory for generative AI
KV cache compression for LLM inference and reinforcement-learning rollout, targeting memory and data-movement bottlenecks while preserving model quality.
About Me
I work on high-performance AI systems through algorithm-architecture-chip co-design, with a focus on the computing and interconnect infrastructure behind modern AI.
I am a Ph.D. student in the ISCL Lab at Nanjing University, advised by Prof. Li Du and Associate Prof. Yuan Du. Before beginning my doctoral research, I worked on algorithm-hardware co-design. I welcome conversations and collaboration around efficient AI computing systems.
Building AI systems across three layers
My Ph.D. research is organized around three connected layers, from algorithms to architecture and system scale. These are forward-looking research directions and are separate from my master's publications below.
Architecture
Algorithm-architecture co-design
High-performance accelerator architectures derived from workload characteristics, with joint optimization across algorithms, dataflow, memory hierarchy, and hardware.
System
AI supernodes and interconnects
Compute and interconnect architectures for tightly coupled AI supernodes, exploring scalable communication and efficient collective execution.
Education
Nanjing University · ISCL Lab
Ph.D. Student
High-performance AI systems.
Nanjing University · ISCL Lab
Master's Student
Algorithm-hardware co-design.
Hunan University
B.Eng. in Integrated Circuits
Undergraduate study in integrated circuits and electronic systems.
Honors & Awards
National Scholarship for Graduate Students
Nanjing University
National Second Prize · East China First Prize
China College IC Competition · Aerospace Microelectronics Cup
National First Prize
China Undergraduate Mathematical Contest in Modeling
National Scholarship for Undergraduate Students · Three consecutive years
Hunan University
News
Recent updatesOur paper MG-PM was published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
Received the National Scholarship for Graduate Students at Nanjing University.
Our paper Elimination of Non-Idealities for Multi-Channel Phased Array Systems with Zero-IF Receiver was published in Journal of Signal Processing Systems.
Won the National Second Prize and East China First Prize in the China College IC Competition.
Selected Publications
Selected work · M.S. stageThe following publications were completed during my master's study. They established my experience in algorithm-hardware co-design and phased-array signal processing, but are not part of the three doctoral research themes above.
2026 MG-PM: A Mixed-Granularity Polynomial Multiplier for High-Efficient Computation Across Variable Degrees
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable mixed-granularity accelerator for efficient polynomial multiplication across variable degrees.
DOI
2024 Elimination of Non-Idealities for Multi-Channel Phased Array Systems with Zero-IF Receiver
Journal of Signal Processing Systems, 96(12), 821-835
A dynamic calibration scheme for channel mismatch and receiver non-idealities in multi-channel phased-array systems.
DOI